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參數(shù)資料
| 型號： | MC68HC05BD5P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 63/112頁 |
| 文件大?。?/td> | 864K |
| 代理商： | MC68HC05BD5P |
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MOTOROLA
7-8
MC68HC05BD3
M-BUS SERIAL INTERFACE
7
7.3.4
M-Bus Status Register (MSR)
The MIF and MAL bits are software clearable; while the other bits are read only.
MCF - Data Transfer Complete
1 (set)
–
A byte transfer has been completed.
0 (clear) –
A byte is being transfer.
When MCF is set, the MIF (M-Bus interrupt) bit is also set. An M-Bus interrupt is generated if the
MIEN bit is set.
MAAS - Addressed as Slave
1 (set)
–
Currently addressed as a slave.
0 (clear) –
Not currently addressed.
This MAAS bit is set when its own specic address (M-Bus Address register) matches the calling
address. When MAAS is set, the MIF (M-Bus interrupt) bit is also set. An interrupt is generated if
the MIEN bit is set. Then CPU needs to check the SRW bit and set its MTX bit accordingly. Writing
to the M-Bus Control register clears this bit.
MBB - Bus Busy
1 (set)
–
M-Bus busy.
0 (clear) –
M-Bus idle.
This bit indicates the status of the bus. When a START signal is detected, MBB is set. When a
STOP signal is detected, it is cleared.
MAL - Arbitration Lost
1 (set)
–
Lost arbitration in master mode.
0 (clear) –
No arbitration lost.
This arbitration lost ag is set when the M-Bus master loses arbitration during a master
transmission mode. When MAL is set, the MIF (M-Bus interrupt) bit is also set. This bit must be
cleared by software.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$001A
MCF
MAAS
MBB
MAL
SRW
MIF
RXAK
1000 0001
TPG
52
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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