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參數(shù)資料
| 型號： | MC68HC05BD5P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 68/112頁 |
| 文件大?。?/td> | 864K |
| 代理商： | MC68HC05BD5P |
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MC68HC05BD3
MOTOROLA
7-13
M-BUS SERIAL INTERFACE
7
LAMAR
BSET
3,MCR
; LAST SECOND, DISABLE ACK
; TRANSMITTING
BRA
NXMAR
ENMASR BCLR
5,MCR
; LAST ONE, GENERATE 'STOP'
; SIGNAL
NXMAR
LDA
MDR
; READ DATA AND STORE
STA
RXBUF
RTI
7.4.5
Generation of a Repeated START Signal
At the end of data transfer, if the master still wants to communicate on the bus, it can generate
another START signal followed by another slave address without rst generating a STOP signal.
A program example is as shown.
RESTART
BCLR
5,MCR
; ANOTHER START (RESTART) IS
BSET
5,MCR
; GENERATED BY THESE TWO
; CONSECUTIVE INSTRUCTIONS
LDA
#CALLING
; GET THE CALLING ADDRESS
STA
MDR
; TRANSMIT THE CALLING
; ADDRESS
7.4.6
Slave Mode
In the slave service routine, the master addressed as slave bit (MAAS) should be tested to check
if a calling of its own address has been received (Figure 7-4). If MAAS is set, software should set
the transmit/receive mode select bit (MTX bit of MCR) according to the R/W command bit (SRW).
Writing to the MCR clears the MAAS automatically. A data transfer may then be initiated by writing
to MDR or a dummy read from MDR.
In the slave transmit routine, the received acknowledge bit (RXAK) must be tested before
transmitting the next byte of data. RXAK, if set indicates the end of data signal from the master
receiver, the slave transmitter must then switch from transmit mode to receive mode by software
and a dummy read must follow to release the SCL line so that the master can generate a STOP
signal.
7.4.7
Arbitration Lost
If more than one master want to acquire the bus simultaneously, only one master can win and the
others will lose arbitration. The losing device immediately switches to slave receive mode by
M-Bus hardware. Its data output to the SDA line is stopped, but internal transmit clock still runs
until the end of the data byte transmission. An interrupt occurs when this dummy byte transmission
TPG
57
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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