參數(shù)資料
型號(hào)： MC68HC05BD5P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 75/112頁(yè)
文件大?。?/td> 864K
代理商： MC68HC05BD5P
MC68HC05BD3
MOTOROLA
8-5
SYNC SIGNAL PROCESSOR
8
a vertical sync pulse is detected, and the content of the Horizontal sync pulse counter is loaded
into the Horizontal Sync Register before the Low Pulse Duration Counter is reset.
Comparator compares the values of the Horizontal Sync Pulse Counter and Horizontal Sync
Register, and gives the equal signal to the Sync Separation Logic.
High Pulse Duration Counter examines the high pulse width of the incoming composite sync
signal. If it is longer than a specic value (8
s or 16 t
CYC), the vertical sync pulse has nished and
nish signal will be given to the Sync Separation Logic.
Sync Separation Logic passes the composite sync signal to the Hsync output, until there is an
“equal” signal from the comparator. The Hsync output will then output a reassembled waveform
by the Sync Insertion Circuit to emulate the HSYNC pulses, and the Vsync output is set to low at
the coming falling edge of the composite signal. After the nish signal has been sensed, the Vsync
output is xed to high, and the Hsync output follows the composite sync input again.
8.1.5
Vertical Sync Pulse Reshaper
For separate sync inputs, the vertical sync pulse width VTTL equals to the incoming vertical sync
input. For composite sync input, the Sync Pulse Reshaper widens the VTTL pulse width by 9.5
s.
8.1.6
Sync Signal Counters
There are two counters (horizontal line counter and vertical frequency counter) to count the
number of horizontal sync pulses and the number of system clock cycles between two vertical
sync pulses. These two data can be read by the CPU to check the signal frequencies and can be
used to determine the video mode. Figure 8-4 shows a more detailed block diagram of these
counters. The 13-bit vertical frequency register encompasses vertical frequency range from
approximately 15Hz to 125KHz. Figure 8-5 shows the vertical frequency counter timing. It
indicates that there will be
±1 count error on the reading from the register for the same vertical
frequency.
8.2
VSYNC Interrupt
The Sync Signal Processor will generate interrupts to the CPU if the VSYNC Interrupt Enable
(VSIE) bit is set, and the I-bit in the Condition Code Register (CCR) is cleared. The interrupt will
occur at each leading edge of VSYNC.
The interrupt vector address is at $3FF8-$3FF9, and the interrupt latch is cleared automatically
by fetching of the interrupt vectors.
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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