參數(shù)資料
型號： MC68HC05C8A
廠商： Motorola, Inc.
英文描述： Microcontrollers
中文描述： 微控制器
文件頁數(shù)： 74/158頁
文件大?。?/td> 773K
代理商： MC68HC05C8A
Serial Communications Interface (SCI)
Technical Data
MC68HC05C8A
MC68HCL05C8A
MC68HSC05C8A
—
Rev. 5.0
74
Serial Communications Interface (SCI)
MOTOROLA
9.5.1.4 Idle Characters
An idle character contains all logic 1s and has no start or stop bits. Idle
character length depends on the M bit in SCCR1. The preamble is a
synchronizing idle character that begins every transmission.
Clearing the TE bit during a transmission relinquishes the PD1/TDO pin
after the last character to be transmitted is shifted out. The last character
may already be in the shift register, or waiting in the SCDR, or in a break
character generated by writing to the SBK bit. Toggling TE from logic 0
to logic 1 while the last character is in transmission generates an idle
character (a preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
9.5.1.5 Transmitter Interrupts
Two sources can generate SCI transmitter interrupt requests:
1.
Transmit data register empty (TDRE)
—
The TDRE bit in the
SCSR indicates that the SCDR has transferred a character to the
transmit shift register. TDRE is a source of SCI interrupt requests.
The transmission complete interrupt enable bit (TCIE) in SCCR2
is the local mask for TDRE interrupts.
2.
Transmission complete (TC)
—
The TC bit in the SCSR indicates
that both the transmit shift register and the SCDR are empty and
that no break or idle character has been generated. TC is a source
of SCI interrupt requests. The transmission complete interrupt
enable bit (TCIE) in SCCR2 is the local mask for TC interrupts.
9.5.2 Receiver
Figure 9-3
shows the structure of the SCI receiver.
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