參數(shù)資料
型號： MC68HC05E1DWR3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 36/86頁
文件大小： 491K
代理商： MC68HC05E1DWR3
CPU Core
Interrupts
MC68HC05E1 — Revision 2.0
General Release Specication
MOTOROLA
CPU Core
41
comes out of a COP reset in the same operating mode it was in when
the COP time-out was generated.
The COP reset function is enabled or disabled by a mask option.
for more information on the COP Watchdog timer.
3.6.4 Illegal Address Reset
When an opcode fetch occurs from an address which is not implemented
in the RAM ($0090–$01FF) or ROM ($0F00–$1FFF), the part is
automatically reset.
3.7 Interrupts
The MCU can be interrupted four different ways: the three maskable
hardware interrupts (IRQ, timer, and CPI) and the nonmaskable
software interrupt instruction (SWI).
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
RTI instruction causes the register contents to be recovered from the
stack and normal processing to resume.
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
NOTE:
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
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