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參數(shù)資料
| 型號： | MC68HC05E1DWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 63/86頁 |
| 文件大小： | 491K |
| 代理商： | MC68HC05E1DWR3 |
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General Release Specication
MC68HC05E1 — Revision 2.0
66
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
MOTOROLA
Timer, Phase-Locked Loop, and Custom Periodic
6.4.1 Phase-Locked Loop Control Register (PLLCR) $07
This read/write register contains the control bits select the PLL
frequency and enable/disable the synthesizer.
Figure 6-5. Phase-Locked Loop Control Register
BCS — Bus Clock Select
When this bit is set, the output of the PLL is used to generate the
internal processor clock. When clear, the internal bus clock is driven
by the crystal (OSC1
÷2). Once BCS has been changed, it may take
up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition.
During the transition, the clock select output will be held low and all
CPU and timer activity will cease until the transition is complete.
Before setting BCS, allow at least a time of tPLLS after PLLON is set.
Reset clears this bit.
AUTO
When set, this bit selects the automatic bandwidth circuitry in the
Phase detect block. When clear, manual bandwidth control is
selected. Reset sets this bit.
NOTE:
The use of automatic bandwidth is not recommended at this time.
BWC — Bandwidth Control
This bit selects high bandwidth control when set, and low bandwidth
control when clear. The low bandwidth driver is always enabled, so
this bit determines whether the high bandwidth driver is on or off.
Bandwidth control is under manual control only when the AUTO bit is
clear. When the AUTO bit is set, BWC acts as a read-only status bit
to indicate which mode has been selected by the internal circuit. On
PLL start-up in automatic mode (AUTO=1), the high bandwidth driver
is enabled (BWC=1) by internal circuitry until the PLL has locked onto
0
AUTO
BWC
PLLON VCOTST
PS1
PS0
BCS
$07
0
101101
0
RESET:
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