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| 型號： | MC68HC05E1DWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 75/86頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MC68HC05E1DWR3 |
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Electrical Specifications
3.3-Volt DC Electrical Characteristics
MC68HC05E1 — Revision 2.0
General Release Specication
MOTOROLA
Electrical Specifications
77
7.7 3.3-Volt DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
ILoad = 10.0 A
ILoad = –10.0 A
VOL
VOH
—
VDD –0.1
—
0.1
—
V
Output High Voltage
(ILoad = –0.2 mA) PA0–PA7, PB0–PB7, PC0–PC3
VOH
VDD –0.3
—
V
Output Low Voltage
(ILoad = 0.4 mA) PA0–PA7, PB0–PB7, PC0–PC3
VOL
—
0.30
V
Input High Voltage
PA0–PA7, PB0–PB7, PD0–PD3, IRQ, RESET, OSC1
VIH
0.7 x VDD
—VDD
V
Input Low Voltage
PA0–PA7, PB0–PB7, PD0–PD3, IRQ, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
XFC Wide Bandwidth
Source
Sink
IOH
IOL
–25
25
–50
50
—
A
XFC Narrow Bandwidth
Source
Sink
IOH
IOL
–-0.5
0.5
–1
1
—
A
Supply Current (see Notes)
Run
fosc = 32.768 kHz, fOP =16.384 kHz
fosc = 2.1 MHz, fOP = 1.0 MHz
Wait
fosc = 32.768 kHz, fOP =16.384 kHz
fosc = 2.1 MHz, fOP = 1.0 MHz
Stop (PLL off)
25
°C
–40
°C to +85 °C (Extended)
IDD
—
60
1.5
30
0.3
1
—
90
2.0
50
0.3
30
120
A
mA
A
mA
A
I/O Ports Hi-Z Leakage Current
PB0–PB7, PC0–PC3, PA0–PA7
IOZ
——
10
A
Input Current
RESET, IRQ, OSC1
IIN
——
1
A
Capacitance
Ports (As Input or Output)
RESET, IRQ
COUT
CIN
—
12
8
pF
NOTES:
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to 70 °C, unless otherwise noted
2. All values shown reect average measurements at midpoint of voltage range at 25
°C.
3. Wait IDD: Only timer and CPI systems active
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source, all inputs 0.2 V from rail; no dc
loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
5. Wait, Stop IDD: All ports congured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc.
6. Stop IDD is measured with OSC1 = VSS.
7. Standard temperature range is 0
°C to 70 °C. Extended temperature range (–40 °C to 85 °C) is available.
8. Wait IDD is affected linearly by the OSC2 capacitance.
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