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參數(shù)資料
| 型號(hào)： | MC68HC05E1DWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 46/86頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MC68HC05E1DWR3 |
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General Release Specication
MC68HC05E1 — Revision 2.0
50
Input/Output Ports
MOTOROLA
Input/Output Ports
4.4 Port B
Port B is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The address of the port B data register is $0001
and the data direction register (DDR) is at address $0005. Reset does
not affect the data registers, but clears the data direction registers,
thereby returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode.
4.5 Port C
Port C is a 4-bit bidirectional port which does not share any of its pins
with other subsystems. The port C data register is at $0002 and the data
direction register (DDR) is at $0006. Reset does not affect the data
registers, but clears the data direction registers, thereby returning the
ports to inputs. Writing a one to a DDR bit sets the corresponding port
bit to output mode.
4.6 Input/Output Programmingf
Ports A, B and C may be programmed as an input or an output under
software control. The direction of the pins is determined by the state of
the corresponding bit in the port data direction register (DDR). Each port
has an associated DDR. Any port A, port B or port C pin is configured as
an output if its corresponding DDR bit is set to a logic one. A pin is
configured as an input if its corresponding DDR bit is cleared to a logic
zero.
At power-on or reset, all DDRs are cleared, which configures all port A,
B, and C pins as inputs. The data direction registers are capable of being
written to or read by the processor. During the programmed output state,
a read of the data register actually reads the value of the output data
latch and not the I/O pin. See Table 4-1 and Figure 4-1.
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