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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 54/124頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
5-1
INTERRUPTS
5
INTERRUPTS
5.1
Introduction
The MC68HC05G1 is capable of handling eight types of interrupt, seven hardware and one
software. The interrupt mask bit (“I” bit in the Condition Code Register), if set, blocks all interrupts
except the software interrupt, SWI. Interrupts such as Timer, RTC, and SPI have several ags
which will cause the interrupt. Interrupt ags are found in “read only” status registers, while their
enables are in associated control registers. They are never mixed in the same register. If the
enable bit is “0”, it blocks the interrupt from occurring but does not inhibit the ag from being set.
A reset clears all enable bits. The general sequence for clearing an interrupt is a software
sequence of reading the status register while the ag is set followed by a read or write of an
associated register (except RTC, IRQ, INT1 and INT2). When any of these interrupts occur, and
if enabled, normal processing is suspended at the end of the current instruction execution. The
state of the machine is pushed onto the stack (see Figure 5-1 for stacking order) and the
appropriate vector points to the starting address of the interrupt service routine (see Table 5-1).
Also, the interrupt mask bit in the Condition Code register is set. This masks further interrupts. At
the completion of the service routine, the software normally contains an RTI instruction which,
when executed, restores the machine state and continues executing the interrupted program.
Figure 5-2 and Figure 5-3 shows the program ow for hardware interrupts.
Note:
The interrupt mask bit (I bit) will be cleared if and only if the corresponding bit stored
on the stack is zero.
TPG
33
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