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| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 60/124頁(yè) |
| 文件大小： | 732K |
| 代理商： | MC68HC05G1B |
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MOTOROLA
5-6
MC68HC05G1
INTERRUPTS
5
Code register is set. This masks further interrupts until the present one is
serviced. The service routine address is specied by the contents of $3FFA
and $3FFB.
INT1 and INT2
When the signal of the external interrupt pin, INT1 or INT2, satises the
condition selected by the INT1N & INT2N in the Miscellaneous Control
register (bits 6 & 7 of address $27) then an external interrupt occurs. The
actual processor interrupt is generated only if the interrupt mask bit of the
Condition Code register is also cleared. When the interrupt is recognized, the
current state of the processor is pushed onto the stack and the interrupt mask
bit in the Condition Code register is set. This masks further interrupts until the
present one is serviced. The service routine address is specied by the
contents of $3FF8 & $3FF9 for INT1, and $3FF4 & $3FF5 for INT2. After
servicing the interrupt, ags are cleared by writing a “1” to the corresponding
bit; otherwise the CPU will keep servicing the interrupt.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt lines. Figure 5-4 shows both a block diagram and timing for the
interrupt lines (IRQ, INT1, INT2) to the processor. The rst method is used if single pulses on the
interrupt line is spaced far enough apart to be serviced. The minimum time between pulses is
equal to the number of cycles required to execute the interrupt service routine plus 21 cycles.
Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine
(an RTI occurs). The second conguration shows several interrupt lines wired-OR to perform the
interrupts at the processor. Thus, if the interrupt lines remain low after servicing one interrupt, the
next interrupt is recognized.
Note:
The internal interrupt latch is cleared in the rst part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during tILIL and serviced
as soon as the I bit is cleared.
5.4.1
External Interrupt Control Register ($25)
INT1E
1 (set)
–
External interrupt INT1 enable
0 (clear) –
External interrupt INT1 disable
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$25
INT2E
INT1E
00-- ----
TPG
38
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