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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 58/124頁 |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
5-5
INTERRUPTS
5
5.2
Hardware Controlled Sequences
The following three functions are not strictly interrupts, however, they are tied very closely to the
interrupts. These functions are RESET, STOP, WAIT.
1) RESET
The RESET input pin causes the program to go to its starting
address. This address is specied by the contents of memory
locations $3FFE and $3FFF. The interrupt mask of the Condition
Code register is also set. Much of the MCU is congured to some
known state as described in Table 4-1.
2) STOP
If the user chooses to use an interrupted RTC, the STOP
instruction causes the oscillator to be turned off and the
processor “sleeps” until an external interrupt (IRQ, INT1 or INT2)
or RESET occurs. If non-interrupted RTC is used, only the
internal processor clock is turned off. See section 7 on Low
Power Modes.
3) WAIT
The WAIT instruction causes all processor clocks to stop, but
leaves the RTC, Timer, and SPI clocks running. This “rest” state
of the processor can be cleared by RESET, an external interrupt
(IRQ, INT1 or INT2), RTC, Timer or SPI interrupt. There are no
special wait vectors for these individual interrupts. See section 7
on Low Power Modes.
5.3
Software Interrupt (SWI)
The software interrupt is an executable instruction. The action of the SWI instruction is similar to
the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the
Condition Code register. The service routine address is specied by the contents of memory
location $3FFC and $3FFD.
5.4
External Interrupts (IRQ, INT1 & INT2)
There are two types of external interrupt in the MC68HC05G1. They can be software congured
for negative-edge or level sensitive triggering.
IRQ
When the signal of the external interrupt pin, IRQ, satises the condition
selected by the IRQN bit in the Miscellaneous Control register (bits 5 of
address $27) then an external interrupt occurs. The actual processor interrupt
is generated only if the interrupt mask bit of the Condition Code register is
also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the Condition
TPG
37
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