參數(shù)資料
型號: MC68HC05G1B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁數(shù): 73/124頁
文件大小: 732K
代理商: MC68HC05G1B
MOTOROLA
6-6
MC68HC05G1
CLOCKS
6
ALE
1 (set)
Alarm interrupt enable
0 (clear) –
Alarm interrupt disable
SECE
1 (set)
Real time clock once a second interrupt enable
0 (clear) –
Real time clock once a second interrupt disable
It should be noted that the ags in the interrupt status register will be set if the corresponding event
is detected, irrespective of the setting of the interrupt enable bits.
Following is an example showing how to use the RTC interrupt:
*Main program
BSET
0,$1D
Enable RTC (once a day) interrupt.
BSET
1,$1D
Enable RTC (alarm) interrupt.
BSET
2,$1D
Enable RTC (once a second) interrupt.
STOP
MCU execute STOP instruction for power
conservation.
*Real time clock interrupt service routine
BRSET
0,$1C,ODAY
This bit is set indicating this is an once a
day RTC interrupt.
BRSET
1,$1C,ALINT
This bit is set indicating this is a RTC
interrupt caused by a match of alarm registers
and real time clock registers.
BRSET
2,$1C,OSEC
This bit is set indicating this is an once a
second RTC interrupt.
ODAY
BSET
0,$1C
Clear this bit so that this once a day
interrupt will not be recognized as a new one
on next RTC interrupt.
JSR
OADAY
Once a day interrupt service routine.
BRSET
1,$1C,ALINT
This bit is set indicating alarm interrupt
also occurs at the same time.
BRSET
2,$1C,OSEC
This bit is set indicating once a second RTC
interrupt also occurs at the same time.
RTCR
RTI
ALINT
BSET
1,$1C
Clear this bit so that this alarm interrupt
will not be recognized as a new one on next
RTC interrupt.
JSR
ALARM
Alarm service interrupt routine.
BRSET
2,$1C,OSEC
This bit is set indicating once a second
interrupt also occurs at the same time.
BRA
RTCR
Return from interrupt.
TPG
48
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