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參數(shù)資料
| 型號： | MC68HC05RC17DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 111/128頁 |
| 文件大?。?/td> | 561K |
| 代理商： | MC68HC05RC17DW |
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Carrier Modulator Transmitter (CMT)
Modulator
MC68HC05RC17 — Rev. 2.0
General Release Specification
MOTOROLA
Carrier Modulator Transmitter (CMT)
83
NON-DISCLOSURE
AGREEMENT
REQUIRED
EIMSK — External Interrupt Mask
1 = IRQ and keyscan interrupts masked
0 = IRQ and keyscan interrupts enabled
The external interrupt mask bit is used to mask IRQ and keyscan
interrupts. This bit is cleared by reset.
EXSPC — Extended Space Enable
1 = Extended space enabled
0 = Extended space disabled
For a description of the extended space enable bit, see 9.5.3
Extended Space Operation. This bit is cleared by reset.
BASE — Baseband Enable
1 = Baseband enabled
0 = Baseband disabled
When set, the BASE bit disables the carrier generator and forces the
carrier output high for generation of baseband protocols. When BASE
is clear, the carrier generator is enabled and the carrier output toggles
at the frequency determined by values stored in the carrier data
registers. See 9.5.1 Time Mode. This bit is cleared by reset. This bit
is not double buffered and should not be written to during a
transmission.
MODE — Mode Select
1 = CMT operates in FSK mode.
0 = CMT operates in time mode.
For a description of CMT operation in time mode, see 9.5.1 Time
FSK Mode. This bit is cleared by reset. This bit is not double buffered
and should not be written to during a transmission.
IE — Interrupt Enable
1 = CPU interrupt enabled
0 = CPU interrupt disabled
A CPU interrupt will be requested when EOC is set if IE was previously
set. If IE is clear, EOC will not request a CPU interrupt.
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