參數(shù)資料
型號: MC68HC11A8VCFU2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 118/158頁
文件大小: 776K
代理商: MC68HC11A8VCFU2
MOTOROLA
10-20
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
TECHNICAL DATA
10
6-7
LDY
6
1
2
3
4
5
6
1
2
3
4
5
1
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
(IX) + Offset
(IX) + Offset + 1
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
(IX) + Offset + 1
Opcode Address
1
1
1
1
1
1
1
1
1
0
0
1
Opcode (Page Select Byte)
($1A)
Opcode (Second Byte) ($EE)
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
Opcode
Index Offset
Irrelevant Data
Register Data (High Byte)
Register Data (Low Byte)
Opcode (Page Select Byte)
($1A)
Opcode (Second Byte) ($EF)
Index Offset
Irrelevant Data
Register Data (High Byte)
Register Data (Low Byte)
Opcode
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
Opcode (Page Select Byte)
Opcode (Second Byte)
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
Opcode ($AD)
Index Offset
Irrelevant Data
First Opcode in Subroutine
Return Address (Low Byte)
Return Address (High Byte)
Opcode
Index Offset
Irrelevant Data
Original Operand Data
Mask Byte
Irrelevant Data
Result Operand Data
Opcode
Index Offset
Irrelevant Data
Original Operand Data
Mask Byte
Branch Offset
Irrelevant Data
6-8
STD, STS, STX
5
6-9
STY
6
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
7
1
2
3
4
5
6
1
2
3
4
5
6
7
1
2
3
4
5
6
7
Opcode Address + 1
Opcode Address + 2
$FFFF
(IX) + Offset
(IX) + Offset + 1
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
(IX) + Offset + 1
$FFFF
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
(IX) + Offset
(IX) + Offset + 1
$FFFF
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Stack Pointer
Stack Pointer – 1
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Opcode Address + 2
$FFFF
(IX) + Offset
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Opcode Address + 2
Opcode Address + 3
$FFFF
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
6-10
ADDD, CPX, SUBD
6
6-11
CPD, CPY
7
6-12
JSR
6
6-13
BCLR, BSET
7
6-14
BRCLR, BRSET
7
Table 10-6 Cycle-by-Cycle Operation — Indexed X Mode (Sheet 2 of 2)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
*The reference number is given to provide a cross-reference to Table 10-1.
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