MOTOROLA
8-4
PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
MC68HC11A8
TECHNICAL DATA
8
Note that the pulse accumulator function shares line 7 of port A. If the DDRA7 bit in
the pulse accumulator control register (PACTL) is set, then port A line 7 is configured
as an output and OC1 can obtain access by setting OC1M bit 7. In this condition if the
PAEN bit in the PACTL register is set, enabling the pulse accumulator input, then OC1
compares cause a write of OC1D bit 7 to an internal latch, and the output of that latch
drives the pin and the pulse accumulator input. This action can then cause the pulse
accumulator to take the appropriate action (pulse count or gate modes).
8.1.7 Output Compare 1 Data Register (OC1D)
This register is used in conjunction with output compare 1 to specify the data which is
to be stored to the affected bits of port A as the result of a successful OC1 compare.
The bits of the OC1D register correspond bit-for-bit with the lines of port A (lines 7 thru
3 only). When a successful OC1 compare occurs, for each bit that is set in OC1M, the
corresponding data bit in OC1D is stored in the corresponding bit of port A. If there is
a conflicting situation where an OC1 compare and another output compare function
occur during the same E cycle with both attempting to alter the same port A line, the
OC1 action prevails.
8.1.8 Timer Control Register 1 (TCTL1)
OM2, OM3, OM4, and OM5 — Output Mode
OL2, OL3, OL4, and OL5 — Output Level
These two control bits (OMx and OLx) are encoded to specify the output action taken
as a result of a successful OCx compare.
7
6
5
4
3
2
0
0
1
0
0
0
0
0
$
1
00D
RESET
OC1D7
0
OC1D6
0
OC1D5
0
OC1D4
0
OC1D3
0
OC1D
7
6
5
4
3
2
1
0
$
1
020
RESET
OM2
0
OL2
0
OM3
0
OL3
0
OM4
0
OL4
0
OM5
0
OL5
0
TCTL1
OMx
0
0
1
1
OLx
0
1
0
1
Action Taken Upon Successful Compare
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one