參數(shù)資料
型號: MC68HC11D3CFN2
廠商: ABILIS SYSTEMS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 121/138頁
文件大?。?/td> 1047K
代理商: MC68HC11D3CFN2
SPI Registers
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
83
Bits 3–0 — Not implemented
Always reads 0
7.7.3 SPI Data I/O Register
The SPI data I/O register (SPDR) is used when transmitting or receiving data on the serial bus. Only a
write to this register initiates transmission or reception of a byte, and this only occurs in the master device.
At the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave
devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte that
caused the overrun, the first SPIF must be cleared by the time a second transfer of data from the shift
register to the read buffer is initiated.
NOTE
SPI is double buffered in and single buffered out.
Address:
$002A
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 7-5. SPI Data I/O Register (SPDR)
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