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參數(shù)資料
| 型號(hào)： | MC68HC11D3CFN2 |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 69/138頁(yè) |
| 文件大?。?/td> | 1047K |
| 代理商： | MC68HC11D3CFN2 |
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Central Processor Unit (CPU)
MC68HC711D3 Data Sheet, Rev. 2.1
36
Freescale Semiconductor
At the end of the interrupt service routine, a return-from interrupt (RTI) instruction is executed. The RTI
instruction causes the saved registers to be pulled off the stack in reverse order. Program execution
resumes at the return address.
Certain instructions push and pull the A and B accumulators and the X and Y index registers and are often
used to preserve program context. For example, pushing accumulator A onto the stack when entering a
subroutine that uses accumulator A and then pulling accumulator A off the stack just before leaving the
subroutine ensures that the contents of a register will be the same after returning from the subroutine as
it was before starting the subroutine.
3.2.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction to be executed. After
reset, the program counter is initialized from one of six possible vectors, depending on operating mode
and the cause of reset.
See Table 3-1.
3.2.6 Condition Code Register (CCR)
This 8-bit register contains:
Five condition code indicators (C, V, Z, N, and H)
Two interrupt masking bits (IRQ and XIRQ)
One stop disable bit (S)
In the M68HC11 CPU, condition codes are updated automatically by most instructions. For example, load
accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the N, Z,
and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to Table 3-2, which shows what condition codes are
affected by a particular instruction.
3.2.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic operation.
The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate
with and through the carry bit to facilitate multiple-word shift operations.
3.2.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V bit is cleared.
3.2.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is 0. Otherwise, the Z
bit is cleared. Compare instructions do an internal implied subtraction and the condition codes, including
Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and
no other condition flags. For these operations, only = and
≠ conditions can be determined.
Table 3-1. Reset Vector Comparison
Mode
POR or RESET Pin
Clock Monitor
COP Watchdog
Normal
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
Test or boot
$BFFE, $BFFF
$BFFC, $FFFD
$BFFA, $FFFB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC711D3CP3 | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC11D3CFN3 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC11D3CFB1 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44 |
| MC68L11D0CFB3 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC11D0CFN2R2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11D3CFN3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11D3CFN4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11D3CFU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11D3CFU1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11D3CFU3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
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