參數(shù)資料
型號： MC68HC11D3CFN2
廠商： ABILIS SYSTEMS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 40/138頁
文件大?。?/td> 1047K
代理商： MC68HC11D3CFN2
MC68L11D0
MC68HC711D3 Data Sheet, Rev. 2.1
134
Freescale Semiconductor
B.2.5 Expansion Bus Timing
Num
Characteristic(1)
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Frequency of operation (E-clock frequency)
fO
dc
1.0
dc
2.0
MHz
1
Cycle time
tcyc
1000
—
500
—
ns
2
Pulse width, E low, PWEL = 1/2 tcyc — 23 ns
PWEL
475
—
225
—
ns
3
Pulse width, E high, PWEH = 1/2 tcyc – 28 ns
PWEH
470
—
220
—
ns
4A
E and AS rise time
tr
—25
—
25
ns
4B
E and AS fall time
tf
—25
—
25
ns
9
Address hold time(2)a, tAH = 1/8 tcyc – 29.5 ns
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tCYC in the above formulas, where applicable:
(a) (1-dc)
× 1/4 tCYC
(b) dc
× 1/4 tCYC
Where:
DC is the decimal value of duty cycle percentage (high time).
tAH
95
—
33
—
ns
12
Non-muxed address valid time to E rise
tAV = PWEL – (tASD + 80 ns)
(2)a
tAV
275
—
88
—
ns
17
Read data setup time
tDSR
30
—
30
—
ns
18
Read data hold time (max = tMAD)tDHR
0
150
0
88
ns
19
Write data delay time, tDDW = 1/8 tcyc + 65.5 ns
(2)a
tDDW
—
195
—
133
ns
21
Write data hold time, tDHW = 1/8 tcyc – 29.5 ns
(2)a
tDHW
95
—
33
—
ns
22
Muxed address valid time to E rise
tAVM = PWEL – (tASD + 90 ns)
(2)a
tAVM
265
—
78
—
ns
24
Muxed address valid time to AS fall
tASL = PWASH – 70 ns
tASL
150
—
25
—
ns
25
Muxed address hold time, tAHL = 1/8 tcyc – 29.5 ns
(2)b
tAHL
95
—
33
—
ns
26
Delay time, E to AS rise, tASD = 1/8 tcyc – 9.5 ns
(2)a
tASD
120
—
58
—
ns
27
Pulse width, AS high, PWASH = 1/4 tcyc – 29 ns
PWASH
220
—
95
—
ns
28
Delay time, AS to E rise, tASED = 1/8 tcyc – 9.5 ns
(2)b
tASED
120
—
58
—
ns
29
MPU address access time(2)a
tACCA = tcyc – (PWEL– tAVM) – tDSR – tf
tACCA
735
—
298
—
ns
35
MPU access time , tACCE = PWEH – tDSR
tACCE
—
440
—
190
ns
36
Muxed address delay (previous cycle MPU read)
tMAD = tASD + 30 ns
(2)a
tMAD
150
—
88
—
ns
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