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參數(shù)資料
| 型號： | MC68HC681P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 22/88頁 |
| 文件大小： | 461K |
| 代理商： | MC68HC681P |
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Operation
3-6
MC68HC681 USER’S MANUAL
MOTOROLA
3
In the multidrop mode, the receiver continuously monitors the received data stream
regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the receiver
ready status bit and loads the character into the FIFO receive holding register stack provided
the received address/data bit is a one (address tag). The received character is discarded if
the received address/data bit is a zero (data tag). If the receiver is enabled, all received
characters are transferred to the CPU by way of the receive holding register stack during
read operations. In either case, the data bits are loaded into the data portion of the FIFO
stack while the address/data bit is loaded into the status portion of the FIFO stack normally
used for parity error (status register bit five). Framing error, overrun error, and break-
detection operate normally regardless of whether the receiver is enabled or disabled.
The address/data bit takes the place of the parity bit and parity is neither calculated nor
checked for characters in this mode. Nevertheless, messages in this mode can still contain
error detection and correction information. One way to provide error detection (if 8-bit
characters are not required) would be to use software to calculate parity and append it to 5-,
6-, or 7-bit characters. Another way to provide error detection for the entire message would
be to use cyclic redundancy checks, or Hamming codes similar to those used in
synchronous protocols, perform the check in software, and append the check character(s)
to the end of the message.
3.5 COUNTER/TIMER
The 16-bit counter/timer (C/T) can operate in a counter mode or a timer mode. In either
mode, customers can program the C/T input (clock source) to come from several sources
and program the C/T output to appear on output port pin OP3. The value (preload value)
stored in the concatenation of the C/T upper register (CTUR) and the C/T lower register
(CTLR) can be from 000116 through FFFF16 and can be changed at any time. In counter
mode, the CPU can start and stop the C/T. This mode allows the C/T to function as a system
stopwatch, a real-time single interrupt generator, or a device watchdog. In timer mode, the
C/T runs continuously; the CPU cannot start or stop it. Instead, the CPU only resets the
C/T interrupt. This mode allows the C/T to be used as a programmable clock source for
channels A and B, or periodic interrupt generator. At power-up and after reset, the C/T
operates in timer mode.
3.5.1 Counter Mode
In counter mode, the C/T counts down from the preload value using the programmed
counter clock source. The counter clock source can be the channel A transmitter clock, the
channel B transmitter clock, the external clock on the X1 pin divided by sixteen, or an
external clock on the input port pin IP2. The CPU can start and stop the counter, and can
read the count value (CUR:CLR) if the counter is stopped. When a read at the start counter
command address is performed, the counter is initialized to the preload value and begins a
countdown sequence. When the counter counts from 000116 to 000016 (terminal count), the
C/T-ready bit in the interrupt status register (ISR[3]) is set.
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