參數(shù)資料
型號： MC68HC681P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 38/88頁
文件大小： 461K
代理商： MC68HC681P
Programming and Register Descriptions
MOTOROLA
MC68HC681 USER’S MANUAL
4-13
4
4.3 REGISTER DESCRIPTION
The following paragraphs provide a detailed description of each register and its function.
4.3.1 Channel A Mode Register 1 (MR1A)
The channel A mode register one (MR1A) is accessed when the channel A mode register
pointer points to MR1. The pointer is set to MR1 by RESET or by a "set pointer" command
applied via command register A. After reading or writing MR1A, the pointer will point to
channel A mode register two (MR2A).
4.3.1.1 CHANNEL A RECEIVER READY-TO-RECIEVE CONTROL — MR1A[7]. This
bit allows the parallel output OP0 to be used as a ready-to-receive indicator (RTRA),
controlled by the channel A receiver. OP0 must first be asserted by setting OPR[0].
MR1A[7] = 1 causes RTRA to be negated on receipt of a valid start bit if the channel A
FIFO is full. RTRA will be reasserted when an empty FIFO position is available. This
feature can be used for flow control to prevent overrun in the receiver by using the RTRA
output signal to control the clear-to-send CTS input of the transmitting device.
4.3.1.2 CHANNEL A RECEIVER-INTERRUPT SELECT - MR1A[6]. This bit selects
either the channel A receiver-ready status (RxRDY) or the channel A FIFO full status
(FFULL) to be used for CPU interrupts. It also causes the selected bit to be output on the
parallel output OP4 if OP4 is programmed as an interrupt output via the output port
configuration register (OPCR).
4.3.1.3 CHANNEL A ERROR MODE SELECT - MR1A[5]. This bit selects the operating
mode of the three FIFO status bits (framing error (FE), parity error (PE), and received
break (RB)) for channel A. In the "character" mode, status provided in the status register
is given on a character-by-character basis and applies only to the character at the top of
the FIFO. In the "block" mode, the status provided in the status register for these bits is
the accumulation (logical OR) of the status for all characters coming to the top of the FIFO
since the last reset error status command for channel A was issued.
4.3.1.4 CHANNEL A PARITY MODE SELECT - MR1A[4:3]. If "with parity" or "force
parity" is selected, a parity bit is added to the transmitted character and the receiver
performs a parity check on incoming data. MR1A[4:3] = 11 selects channel A to operate
in the multidrop mode as described in Section 3.4 Multidrop Mode.
4.3.1.5 CHANNEL A PARITY TYPE SELECT - MR1A[2]. This bit selects the parity type
(odd or even) in "with parity" mode; the polarity of the forced parity bit in "force parity"
mode; or the state of the address/data tag bit in “multidrop” mode. It has no effect in "no
parity" mode.
4.3.1.6 CHANNEL A BITS-PER-CHARACTER SELECT - MR1A[1:0]. This field selects
the number of data bits per character to be transmitted and received. The character length
does not include the start, parity, and stop bits.
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