參數(shù)資料
型號: MC68HC705E6
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: HCMOS Microcontroller Unit
中文描述: HCMOS微控制器
文件頁數(shù): 60/140頁
文件大小: 788K
代理商: MC68HC705E6
Programmable Timer
MC68HC05E6 — Rev. 1.0
Programmable Timer
All bits of the output compare register are readable and writable and are
not altered by the timer hardware or reset. If the compare function is not
needed, the two bytes of the output compare register can be used as
storage locations.
Timer during WAIT mode
In WAIT mode all CPU action is suspended, but the programmable timer
continues counting. An interrupt from an input capture, an output
compare or a timer overflow, if enabled, will cause the processor to exit
WAIT mode.
Timer during STOP mode
In the STOP mode all MCU clocks are stopped, hence the timer stops
counting. If STOP is exited by an interrupt, the counter retains the last
count value. If the device is reset, then the counter is forced to $FFFC.
During STOP, if at least one valid input capture edge occurs at the TCAP
pin, the input capture detect circuit is armed. This does not set any timer
flags nor wake up the MCU. When the MCU does wake up, however,
there is an active input capture flag and data from the first valid edge that
occurred during the STOP period. If the device is reset to exit STOP
mode, then no input capture flag or data remains, even if a valid input
capture edge occurred.
Timer state diagrams
The relationships between the internal clock signals, the counter
contents and the status of the flag bits are shown in the following
diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
10-ptimer
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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