July 16, 1999
GENERAL RELEASE SPECIFICATION
MEMORY
REV 2.1
2-3
2.4
I/O REGISTERS SUMMARY
ADDR
REGISTER
Port A Data
PORTA
Port B Data
PORTB
Timer1 Capture Control
T1CC
R/W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$0000
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0001
0
0
PB5
PB4
PB3
PB2
PB1
PB0
$0002
TCAPS
$0003
Unimplemented
$0004
Port A Data Direction
DDRA
Port B Data Direction
DDRB
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
$0005
SLOWE
0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
$0006
Unimplemented
$0007
Unimplemented
$0008
MFT Ctrl/Status
TCSR
MFT Counter
TCR
IRQ Control/Status
ICSR
TOF
RTIF
TOFE
RTIE
0
0
RT1
RT0
TOFR
TMR3
RTIFR
TMR2
$0009
TMR7
TMR6
TMR5
TMR4
TMR1
TMR0
$000A
IRQE
IRQE1
0
0
R
IRQF
IRQF1
0
0
IRQR
IRQR1
$000B
Unimplemented
$000C
Unimplemented
$000D
Unimplemented
$000E
Unimplemented
$000F
Unimplemented
unimplemented bits
reserved bits
Figure 2-3. I/O Registers $0000-$000F
F
Freescale Semiconductor, Inc.
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