參數(shù)資料
型號： MC68HC705J5A
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 8-bit microcontroller units
中文描述： 8位微控制器單元
文件頁數(shù)： 63/106頁
文件大?。?/td> 670K
代理商： MC68HC705J5A
July 16, 1999
GENERAL RELEASE SPECIFICATION
16-BIT TIMER
REV 2.1
9-5
NOTE
To prevent interrupts from occurring between readings of the ACNTH and ACNTL,
set the I bit in the condition code register (CCR) before reading ACNTH and clear
the I bit after reading ACNTL.
9.3
INPUT CAPTURE REGISTERS
Figure 9-6. Timer Input Capture Block Diagram
The input capture function is a technique whereby an external signal (connected
to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-
ble to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
NOTE
Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0
DDR or Data Register can cause an unwanted TCAP interrupt. This can be
avoided by clearing the ICIE bit before changing the configuration of PB0, and
clearing any pending interrupts before enabling ICIE.
The signal on the TCAP pin is first directed to a schmitt trigger or a voltage
comparator as shown in
Figure 9-8
. Setting the TCAPS bit to “1” will enable the
comparator and the V
DD
/2 reference voltage.
I
ICH ($14)
16-BIT COUNTER
÷
4
INTERNAL
CLOCK
(f
OSC
÷
TIMER1
INTERRUPT
TIMER1 CONTROL REG.
REQUEST
INPUT CAPTURE (ICF)
RESET
ICL ($15)
I
TIMER1 STATUS REG.
$12
$13
INTERNAL
DATA
BUS
(
READ
ICH
READ
ICL
LATCH
I
EDGE
SELECT
& DETECT
LOGIC
I
INTERNAL
DATA
BUS
SIGNAL
CONDITIONING
PB0/
TCAP
TCAPS
(bit7 at $02)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關代理商/技術參數(shù)
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