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參數(shù)資料
| 型號： | MC68HC705J5A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 8-bit microcontroller units |
| 中文描述： | 8位微控制器單元 |
| 文件頁數(shù)： | 48/106頁 |
| 文件大?。?/td> | 670K |
| 代理商： | MC68HC705J5A |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
INPUT/OUTPUT PORTS
For More Information On This Product,
Go to: www.freescale.com
MC68HC05J5A
REV 2.1
7-4
7.3
PORT B
Port B is a 6-bit bidirectional port which functions as shown in
Figure 7-3
. Only
PB1 and PB2 are of open-drained type. Each Port B pin is controlled by the corre-
sponding bits in a data direction register, a data register and a pulldown/up regis-
ter. The Port B Data Register is located at address $0001. The Port B Data
Direction Register (DDRB) is located at address $0005. The Port B Pulldown/up
Register (PDURB) is located at address $0011. Reset clears the DDRB and the
PDURB. The Port B Data Register is unaffected by reset.
Please note that only PB0 and PB1 pins are bonded out in the 16-pin package
type. Actually, the PB1 and PB2 I/O port lines are short and bonded to the PB1 on
the 16-pin package. Both PB1 and PB2 are of open-drained type, capable of typi-
cally sinking 25mA current at V
OL
0.5V max. In order to constitute a single pin
capable of typically sinking 50mA, both PB1 and PB2 have to be written with the
same value at the same write cycle.
Figure 7-3. Port B I/O Circuitry
Port Pin PB0 is shared with TCAP input of the 16-Timer input capture function.
The input capture function can be programmed for a positive edge or the negative
edge TCAP input. When an expected edge is generated on this pin, the counter
value at that moment will be captured into a capture register. For the details about
this feature please refer to the
Section 9
.
7.3.1 Port B Data Register
All Port B I/O pins have a corresponding bit in the Port B Data Register. When a
Port B pin is programmed as output the corresponding data register bit
determines the logic state of the output pin. When a Port B pin is programmed as
input, any read from the Port B Data Register will return the logic state of the
Write $0011
Read $0001
Write $0001
Read $0005
Write $0005
Internal HC05
Data Bus
100 A
Pulldown
Data
Register Bit
Output
Mask Option
(Software Pulldown/up Inhibit)
Reset
(RST)
Data Direction
Register Bit
Pulldown/up
Register Bit
VDD
30K
Pullup
Note1: All the I/O port pins may have either pullup or pulldown device.
Note2: PB1 and PB2 output drivers are the open-drained type
F
Freescale Semiconductor, Inc.
n
.
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