
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
45
Chapter 8
Capture/Compare Timer
8.1 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure
of the capture/compare subsystem.
Figure 8-1. Capture/Compare Timer Block Diagram
INPUT
CAPTURE
REGISTER
CLOCK
INTERNAL BUS
OUTPUT
COMPARE
REGISTER
HIGH
BYTE
LOW
BYTE
$16
$17
÷4
INTERNAL
PROCESSOR
16-BIT FREE
RUNNING
COUNTER
ALTERNATE
REGISTER
8-BIT
BUFFER
HIGH
BYTE
LOW
BYTE
$1A
$1B
$18
$19
HIGH
BYTE
LOW
BYTE
$14
$15
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
EDGE
DETECT
CIRCUIT
TIMER
STATUS
REG.
ICF OCF TOF $13
ICIE
IEDG OLVL
OUTPUT
LEVEL
REG.
RESET
TIMER
CONTROL
REG.
$12
OUTPUT
LEVEL
(TCMP)
INTERRUPT CIRCUIT
TOIE
OCIE
EDGE
INPUT
(TCAP)
D
CLK
C
Q