參數(shù)資料
型號： MC68HCL05C8AB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PDIP42
封裝： PLASTIC, SDIP-42
文件頁數(shù)： 44/116頁
文件大?。?/td> 781K
代理商： MC68HCL05C8AB
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
33
Chapter 5
Resets
5.1 Introduction
The microcontroller unit (MCU) can be reset three ways:
1.
Initial power-on reset function
2.
Active low input to the RESET pin
3.
Computer operating properly (COP) reset
5.2 Power-On Reset (POR)
An internal reset is generated on power-up to allow the internal clock generator to stabilize. The power-on
reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply
voltage. There is a 4064 internal processor clock cycle (tCYC) oscillator stabilization delay after the
oscillator becomes active. If the RESET pin is low after the end of this 4064-cycle delay, the MCU will
remain in the reset condition until RESET goes high.
For additional information, refer to Figure 13-8. Power-On Reset Timing Diagram.
5.3 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a period of one and one-half machine
cycles (tRL).
5.4 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature as a mask option. The COP is implemented with an 18-bit
ripple counter. This provides a timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP should
time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on
reset (POR) or external reset.
5.4.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPC bit. This action will reset the counter and
begin the timeout period again. The COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will
result in the user defined ROM data at that location.
5.4.2 COP During Wait Mode
The COP will continue to operate normally during wait mode. The software should pull the device out of
wait mode periodically and reset the COP by writing to the COPC bit to prevent a COP reset.
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