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參數(shù)資料
| 型號(hào)： | MC68HCL05C8AB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP42 |
| 封裝： | PLASTIC, SDIP-42 |
| 文件頁(yè)數(shù)： | 48/116頁(yè) |
| 文件大小： | 781K |
| 代理商： | MC68HCL05C8AB |
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MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
37
Chapter 7
Input/Output (I/O) Ports
7.1 Introduction
The MC68HC05C8A has three 8-bit input/output (I/O) ports.These 24 port pins are programmable as
either inputs or outputs under software control of the data direction registers. Port D does not have a data
direction register, and its seven pins are input only with the exception of certain serial communications
(SCI)/serial peripheral interface (SPI) functions.
NOTE
To avoid a glitch on the output pins, write data to the I/O port data register
before writing a 1 to the corresponding data direction register.
7.2 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port
A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the
data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to
a DDR bit sets the corresponding port bit to output mode.
7.3 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register
(DDR) is at $0005. Reset does not affect the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port pin to output mode. Each
of the port B pins has a mask programmable interrupt capability. This interrupt option also enables a
pullup device when the pin is configured as an input (see Figure 7-1). The edge or edge and level
sensitivity of the IRQ pin also will pertain to the enabled port B pins via mask options. Be careful when
using port B pins that have the pullup enabled. Before switching from an output to an input, the data
should be preconditioned to a 1 to prevent an interrupt from occurring.
Figure 7-1. Port B Pullup Option
PB0
VDD
DDR BIT
FROM ALL OTHER PORT B PINS
IRQ
SCHMITT
TRIGGER
TO INTERRUPT
LOGIC
MASK OPTION
NORMAL PORT CIRCUITRY
AS SHOWN IN Figure 7-2
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