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參數(shù)資料
| 型號(hào)： | MC68HSC05C12AB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SHRINK, PLASTIC, DIP-42 |
| 文件頁(yè)數(shù)： | 103/156頁(yè) |
| 文件大小： | 3848K |
| 代理商： | MC68HSC05C12AB |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Input/Output (I/O) Ports
General Release Specification
MC68HC05C12A — Rev. 3.0
Input/Output (I/O) Ports
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001
and the data direction register (DDR) is at $0005. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port pin to output mode. Each of the port B pins has a
mask programmable interrupt capability. This interrupt option also
enables a pullup device when the pin is configured as an input (see
Figure 7-1). The edge or edge and level sensitivity of the IRQ pin also
will pertain to the enabled port B pins via mask options. Be careful when
using port B pins that have the pullup enabled. Before switching from an
output to an input, the data should be preconditioned to a one to prevent
an interrupt from occurring.
Figure 7-1. Port B Pullup Option
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002
and the data direction register (DDR) is at $0006. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode. PC7 has a high current sink and
source capability.
PB0
VDD
DDR BIT
NORMAL PORT CIRCUITRY
AS SHOWN IN
FROM ALL OTHER PORT B PINS
IRQ
SCHMITT
TRIGGER
TO INTERRUPT
LOGIC
MASK OPTION
FIGURE 7-2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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