參數(shù)資料
型號: MC68HSC05C12AB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
封裝: SHRINK, PLASTIC, DIP-42
文件頁數(shù): 142/156頁
文件大?。?/td> 3848K
代理商: MC68HSC05C12AB
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Peripiheral Interface (SPI)
General Release Specification
MC68HC05C12A Rev. 3.0
Serial Peripiheral Interface (SPI)
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.6 SPI Registers
Three registers in the SPI provide control, status, and data storage
functions. These registers are called the serial peripheral control register
(SPCR), serial peripheral status register (SPSR), and serial peripheral
data I/O register (SPDR) and are described in the following paragraphs.
I/O PORT
SPDR ($000C)
SPI SHIFT REGISTER
PD3/MOSI
PD2/MISO
PD4/SCK
MASTER MCU
SLAVE MCU
SS
PD5
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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