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| 型號(hào)： | MC68HSC05C12AB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SHRINK, PLASTIC, DIP-42 |
| 文件頁(yè)數(shù)： | 119/156頁(yè) |
| 文件大?。?/td> | 3848K |
| 代理商： | MC68HSC05C12AB |
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Serial Communications Interface (SCI)
SCI Operation
MC68HC05C12A — Rev. 3.0
General Release Specification
Serial Communications Interface (SCI)
NON-DISCLOSURE
AGREEMENT
REQUIRED
9.5 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial
communication between the MCU and remote devices, including other
MCUs. The SCI’s transmitter and receiver operate independently,
although they use the same baud-rate generator. The following
paragraphs describe the operation of the SCI transmitter and receiver.
9.5.1 Transmitter
Figure 9-2 shows the structure of the SCI transmitter.
9.5.1.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCCR1) determines character length.
When transmitting 9-bit data, bit T8 in SCCR1 is the ninth bit (bit 8).
9.5.1.2 Character Transmission
During transmission, the transmit shift register shifts a character out to
the PD1/TDO pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register.
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then
writing data to the SCDR begins the transmission. At the start of a
transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out,
the control logic transfers the SCDR data into the shift register. A logic 0
start bit automatically goes into the least significant bit position of the
shift register, and a logic 1 stop bit goes into the most significant bit
position.
When the data in the SCDR transfers to the transmit shift register, the
transmit data register empty (TDRE) flag in the SCI status register
(SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
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