參數(shù)資料
型號(hào)： MC68HSC05C8AP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 63/116頁
文件大小： 781K
代理商： MC68HSC05C8AP
Serial Communications Interface (SCI)
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
50
Freescale Semiconductor
Clearing the TE bit during a transmission relinquishes the PD1/TDO pin after the last character to be
transmitted is shifted out. The last character may already be in the shift register, or waiting in the SCDR,
or in a break character generated by writing to the SBK bit. Toggling TE from logic 0 to logic 1 while the
last character is in transmission generates an idle character (a preamble) that allows the receiver to
maintain control of the PD1/TDO pin.
9.4.1.5 Transmitter Interrupts
Two sources can generate SCI transmitter interrupt requests:
1.
Transmit data register empty (TDRE) — The TDRE bit in the SCSR indicates that the SCDR has
transferred a character to the transmit shift register. TDRE is a source of SCI interrupt requests.
The transmission complete interrupt enable bit (TCIE) in SCCR2 is the local mask for TDRE
interrupts.
2.
Transmission complete (TC) — The TC bit in the SCSR indicates that both the transmit shift
register and the SCDR are empty and that no break or idle character has been generated. TC is a
source of SCI interrupt requests. The transmission complete interrupt enable bit (TCIE) in SCCR2
is the local mask for TC interrupts.
9.4.2 Receiver
Figure 9-3 shows the structure of the SCI receiver.
9.4.2.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit 8).
9.4.2.2 Character Reception
During reception, the receive shift register shifts characters in from the PD0/RDI pin. The SCI data register
(SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character is
transferred to the SCDR, setting the receive data register full (RDRF) flag. The RDRF flag can be used
to generate an interrupt.
9.4.2.3 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup enable (RWU) bit in SCI control
register 2 (SCCR2) puts the receiver into a standby state during which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the receiver out of the standby state:
1.
Idle input line condition — If the PD0/RDI pin is at logic 1 long enough for 10 or 11 logic 1s to shift
into the receive shift register, receiver interrupts are again enabled.
2.
Address mark — If a logic 1 occurs in the most significant bit position of a received character,
receiver interrupts are again enabled.
The state of the WAKE bit in SCCR1 determines which of the two conditions wakes up the MCU.
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