參數(shù)資料
型號: MC68L11F1CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 130/174頁
文件大小: 981K
代理商: MC68L11F1CFN3
MC68HC11F1
OPERATING MODES AND ON-CHIP MEMORY
MOTOROLA
TECHNICAL DATA
4-21
*PCSEN is set out of reset in expanded modes and cleared in single-chip modes.
IO1EN — I/O Chip Select 1 Enable
0 = CSIO1 is disabled and port G bit 5 is general-purpose I/O.
1 = CSIO1 is enabled and uses port G bit 5.
IO1PL — I/O Chip Select 1 Polarity Select
0 = CSIO1 active low
1 = CSIO1 active high
IO2EN — I/O Chip Select 2 Enable
0 = CSIO2 is disabled and port G bit 4 is general-purpose I/O.
1 = CSIO2 is enabled and uses port G bit 4.
IO2PL — I/O Chip Select 2 Polarity Select
0 = CSIO2 active low
1 = CSIO2 active high
GCSPR — General-Purpose Chip Select Priority
0 = Program chip select has priority over general-purpose chip select
1 = General-purpose chip select has priority over program chip select
PCSEN — Program Chip Select Enable
This bit is set out of reset in expanded modes and cleared in single-chip modes.
0 = CSPROG disabled and port G bit 7 available as general-purpose I/O
1 = CSPROG enabled out of reset and uses port G bit 7 pin
PSIZA, PSIZB — Program Chip Select Size (A or B)
GA[15:10] — General-Purpose Chip Select Base Address
GA[15:10] correspond to MCU address bits ADDR[15:10] and select the starting ad-
dress of the general-purpose chip select's address range. Which bits are valid de-
pends upon the size selected by GSIZA–GSIZC in CSGSIZ register. Refer to the
following table and to Figure 4-4.
CSCTL — Chip Select Control
$105D
Bit 7
654321
Bit 0
IO1EN
IO1PL
IO2EN
IO2PL
GCSPR
PCSEN*
PSIZA
PSIZB
RESET:
00000
0
Table 4-9 Program Chip Select Size Control
PSIZA
PSIZB
Size (Bytes)
Address Range
0
64 K
$0000–$FFFF
0
1
32 K
$8000–$FFFF
1
0
16 K
$C000–$FFFF
1
8 K
$E000–$FFFF
CSGADR — General-Purpose Chip Select Address Register
$105E
Bit 7
654321
Bit 0
GA15
GA14
GA13
GA12
GA11
GA10
RESET:
0000000
0
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