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| 型號(hào)： | MC68MH360AI25L |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 129/158頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 25MHZ 240-FQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | M683xx |
| 處理器類(lèi)型： | M683xx 32-位 |
| 速度： | 25MHz |
| 電壓： | 5V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-FQFP（32x32） |
| 包裝： | 托盤(pán) |
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QMC Supplement
1—
—
2
W
Wrap (nal buffer descriptor in table)
0 This is not the last buffer descriptor in the RxBD table.
1 This is the last buffer descriptor in the RxBD table. After this buffer is used, the CPM receives
incoming data into the rst buffer descriptor in the table (the buffer descriptor pointed to by
RBASE). The number of RxBDs in this table is programmable and is determined only by the
wrap bit and by the space constraints of the dual-ported RAM.
3
I
Interrupt
0 The RXB bit will not be set after this buffer has been used, but RXF operation remains
unaffected.
1 The RXB bit (and/or the RXF bit in HDLC mode) of the interrupt table entry will be set when
this buffer has been used by the HDLC controller. These two bits may cause interrupts (if
enabled).
4
L
Last-in-frame (HDLC mode only)—The HDLC controller sets L when this buffer is the last in a
frame. This implies the receipt of a closing ag or reception of an error, in which case one or more
of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame octets to
the data length eld.
0 This buffer is not the last in a frame.
1 This buffer is the last in a frame.
5
F
First-in-frame—The controller sets this bit when this buffer is the rst in a frame.
0 The buffer is not the rst in a frame.
1 The buffer is the rst in a frame.
6
CM
Continuous Mode
0 Normal operation.
1 The empty bit is not cleared by the CPM after this buffer descriptor is closed, allowing the
associated data buffer to be overwritten automatically when the CPM next accesses this
buffer descriptor. The empty bit is not cleared if an error occurs during reception. The user
must terminate continuous mode by clearing this bit.
7—
—
8
UB
User bit—The CPM never touches, sets, or clears this user-dened bit. The user determines how
this bit is used. For example, it can be used to signal between higher level protocols whether a
buffer has been processed by the CPU.
9—
—
10
LG
Rx frame length violation (HDLC mode only)—A frame length greater than the maximum value
was received in this channel. Only the maximum-allowed number of bytes, MFLR rounded to the
nearest higher longword alignment, are written to the data buffer. This event is recognized as
soon as the MFLR value is exceeded when data is long-word-aligned. When data is not long-
word-aligned, this interrupt occurs when the SDMA writes 32 bits to memory. The worst-case
latency from MFLR violation until detected is 3-byte timings for this channel. When MFLR
violation is detected, the receiver is still receiving even though the data is discarded. The buffer is
closed when a ag is detected, and this is considered to be the closing ag for this buffer. At this
point, LG = 1 and an interrupt may be generated. The length eld for this buffer includes
everything between the opening ag and this last identied ag.
Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions (Continued)
Field
Name
Description
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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.
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