參數(shù)資料
型號： MC68MH360AI25L
廠商： Freescale Semiconductor
文件頁數(shù)： 87/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 240-FQFP
標準包裝： 24
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 240-BFQFP
供應商設備封裝： 240-FQFP（32x32）
包裝： 托盤
QMC Supplement
2.1.4 TSATRx/TSATTx Channel Pointers
The channel pointers are 12-bit pointers to the channel-specic parameters in the internal
dual-ported RAM. These should not be confused with TSATRx/TSATTx pointers as
described in Section 2.1.3, “TSATRx/TSATTx Pointers and Time Slot Assignment Table.”
The 6 most-signicant bits of the address are taken from the time slot assignment table. For
the MH360, the most-signicant bit must be zero as the addressing range is only 2 Kbytes.
The 6 least-signicant bits are zero, mapping out a 64-byte area for each of the channel-
specic parameters. The channel-specic parameters are common for Rx and Tx. For 32-
channel support, 2 Kbytes of dual-ported RAM is required (32 * 64), and for 64-channel
support, 4 Kbytes of dual-ported RAM is required (64 * 64). In most cases, time slot 0
channel pointer will address the base of dual-ported RAM for logical channel 0, and time
slot 1 channel pointer would address the base of dual-ported RAM + 4 for logical channel 1.
In Figure 2-2, time slot 5 channel pointer addresses logical channel 5, requiring the channel
pointer being set to 0b000101.
NOTE
It is possible to concatenate multiple time slots to one logical
channel. This is achieved by setting the channel pointers of the
grouped time slots to the same logical channel.
2.1.5 Logical Channel TBASE and RBASE
TBASE and RBASE are within the channel-specic parameters. TBASE is the Tx buffer
descriptor base address, and RBASE is the Rx buffer descriptor base address. These 16-bit
offsets from MCBASE point to individual logical channel’s buffer descriptors located
within the buffer descriptor table. Note that there are individual TBASE and RBASE values
for each logical channel.
2.1.6 MCBASE
MCBASE is located in the global multichannel parameters. Each SCC has a unique
MCBASE value pointing to the base of the SCC’s buffer descriptor table in external
memory. For example, the address of logical channel ve’s Tx buffer descriptor table is
MCBASE + logical channel ve TBASE.
2.1.7 Buffer Descriptor Table
A buffer descriptor table for each SCC is located in a 64-Kbyte area of external memory.
This block size is determined by the TBASE and RBASE addressing range. The memory
segment must be long-word-aligned but can start anywhere in memory. Each SCC has a
maximum of 16,384 (64 Kbytes memory
÷ 4-byte pointers) buffers. For a 32-channel
implementation, each logical channel has a maximum of 256 (16,384 / (32 * 2)) buffers for
receive and 256 buffers for transmit. For each logical channel, there is a circular queue with
programmable start address and length.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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