參數(shù)資料
型號: MC68MH360VR33L
廠商: Freescale Semiconductor
文件頁數(shù): 126/158頁
文件大小: 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 44
系列: M683xx
處理器類型: M683xx 32-位
速度: 33MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
Contents
v
CONTENTS
Paragraph
Number
Title
Page
Number
5.3.4
MC68MH360 Configured for QMC and Ethernet.........................................5-20
Chapter 6
QMC Initialization
6.1
Initialization Steps................................................................................................6-1
6.2
68MH360 T1 Example.......................................................................................6-10
6.3
Restarting the Transmitter..................................................................................6-17
6.4
Restarting the Receiver ......................................................................................6-17
6.5
Disabling Receiver and Transmitter...................................................................6-17
6.6
Debugging Hints ................................................................................................6-17
6.6.1
Pointer Registers ............................................................................................6-17
6.6.2
State Registers ................................................................................................6-18
Chapter 7
Features Deleted in MC68MH360
Chapter 8
Performance
8.1
Common Channel Combinations .........................................................................8-1
8.2
CPM Loading .......................................................................................................8-2
8.3
Bus Latency and Peak Load .................................................................................8-5
Chapter 9
Multi-Subchannel (MSC) Microcode
9.1
MSC Microcode Features.....................................................................................9-1
9.2
MSC Microcode Operation ..................................................................................9-2
9.3
Programming the MSC Protocol ..........................................................................9-3
9.4
MSC Subchanneling Example .............................................................................9-6
9.5
QMC Memory Organization ................................................................................9-7
9.6
Multi-Subchannel Initialization............................................................................9-8
Appendix A
68360 Bit Numbering
A.1
Time Slot Assignment Table............................................................................... A-1
A.2
Registers in HDLC Mode.................................................................................... A-3
A.3
Registers in Transparent Mode ........................................................................... A-4
A.4
Command Register.............................................................................................. A-4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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