參數(shù)資料
型號(hào)： MC68MH360VR33L
廠商： Freescale Semiconductor
文件頁數(shù)： 38/158頁
文件大小： 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
Therefore, a 50-MHz MPC860MH will be needed to run 64 channels of HDLC on
one device.
B.2 860MH-Related Questions
Q: Is Ethernet only available on SCC1 for both 860EN and 860MH?
A: Ethernet is available on any channel. We recommend it on SCC1 due to its larger
FIFO.
Q: How is 64-channel QMC implemented on the 50-MHz 860MH? What is the serial
speed of the TDM channels?
A: Use two SCCs running 32-channel QMC protocol. Each channel is assumed to be
64-Kbps, like a normal time slot on a T1/E1 line, giving an aggregate rate of 4 Mbps
(that is, twice the E1 rate).
Q: Does running transparent-mode processing on the QMC channels decrease the load
on the CPM?
A: CPM loading in transparent mode is not signicantly different from the loading in
HDLC mode; therefore, performance will be the same.
Q: How many channelized T1/E1 ports does the 860MH support? (where E1 is thirty-
two 64-Kbps channels and T1 is 24 channels)
A: With respect to running multiple channels of HDLC, the major limitation of the
current 860MH is clock frequency. A 25-MHz part can run only 32 HDLC channels,
while a 50-MHz part can run 64 channels. At this point, however, the size of the
dual-ported RAM limits the number of HDLC channels to 64.
The MPC860 also has just two time slot assigners. Therefore, it can directly
terminate at most two T1s or E1s.
Q: How is the 860MH congured to support more than 32 channels.
A: The QMC protocol for the 860MH can be used to support more than 32 HDLC
channels in three ways:
In one method, use shared transmit/receive channel routing on one SCC to run
the QMC protocol linking the maximum of 64 time slots of a single multiplexed
line to 64 separate logical channels.
In another method, run the QMC protocol on two separate SCCs, each with its
own set of parameters. With this method, two separate E1s can be routed to the
two separate SCCs. It is not possible, however, to share channels from both E1s
at random between the SCCs. (One E1 will map to the 32 logical channels of one
SCC.)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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