參數(shù)資料
型號： MC68MH360VR33L
廠商： Freescale Semiconductor
文件頁數(shù)： 99/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 2. QMC Memory Organization
2.4.1.1 CHAMR—Channel Mode Register (HDLC)
The channel mode register is a word-length, host-initialized register. Figure 2-7 shows the
channel mode register for HDLC operation.
Notes: 1. All bits that are dened as reserved should be cleared (0).
2. For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 2-7. CHAMR—Channel Mode Register (HDLC)
22
MFLR
16
Maximum frame length register (host-initialized)—Denes the longest expectable
frame for this channel. Its maximum value is 64 Kbytes. The remainder of a frame
which is larger than MFLR is discarded and a ag in the last frame’s BD is set (LG).
An interrupt request (RXF and RXB) might be generated depending on the
interrupt mask. The frame length is considered to be everything between ags,
including CRC. MFLR is checked every long word, but the content may be on any
number of bytes. If MFLR is set to 5 for example, checking is done when 8 bytes
have been received. At this point, the SDMA transfers the long word to memory,
and all 8 bytes will be in the receive buffer. Also at this point the MFLR violation
(>5) is detected and the interrupt may be generated.
No more data will be written into this buffer when the MFLR violation is detected.
24
RSTATE
32
Rx internal state —Initialize to 0x3900
_0000 FC=9, Motorola mode for MH360 or
initialize to 0x3100
_0000 AT=1, Motorola mode for 860MH. See Section 2.4.1.4,
“RSTATE—Rx Internal State (HDLC),” for more information.
28
—
32
Rx internal data pointer—Points to current address of specic channel.
2C
RBPTR
16
Rx buffer descriptor pointer (host-initialized to RBASE prior to operation or due to a
fatal error)—Contains the offset from MCBASE to the current receive buffer. See
Table 2-1. MCBASE + RBPTR gives the address for the BD in use.
2E
—
16
Rx internal byte count—Per Channel: Number of remaining bytes in buffer
30
RPACK
32
(Rx Temp) Packs 4 bytes to 1 long word before writing to buffer.
34
ZDSTATE
32
Zero deletion machine state—(Host-initialized to 0x0000
_0080 in HDLC mode,
0x1800
_0080 in transparent mode, prior to operation and after a fatal Rx error
(global overrun, busy) before channel initialization.)—Contains the previous state
of zero deletion state machine.
The middle 2 bytes, represented by zeros in the initialization value above, hold the
received pattern during reception. A window of 16 bits shows the history of what is
received on this logical channel. More information is given in the application note
section.
38
RCRC
32
Temp receive CRC—Temp value of CRC calculation result
3C
MAX_cnt
16
Max_length counter—Count length remaining
3E
TMP_MB
16
Temp—Holds MIN(MAX_cnt, Rx internal byte count)
0
123456789
10
11
12
13
14
15
MODE
0
IDLM
ENT
RESERVED
POL
CRC
0
RESERVED
NOF
Reset:
0
000000000000000
Table 2-4. Channel-Specific HDLC Parameters (Continued)
Offset
Name
Width
(Bits)
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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