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| 型號(hào)： | MC68MH360VR33L |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 26/158頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | M683xx |
| 處理器類(lèi)型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤(pán) |
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Chapter 9. Multi-Subchannel (MSC) Microcode
Table 9-2 describes the elds in the time slot assignment table for transmit (TSATTx) for
MSC operation.
L
Last bit—Identies the last subchannel in a time slot.
0 This is not the last subchannel in the time slot.
1 This is the last sub channel within an 8-bit time slot.The RISC processor handles the next time
slot transferred from the TSA in the next request.
Rx channel
pointer
This eld of the TSATRx entry identies the data channel that is routed to this time slot. The actual
channel pointer is 11 bits long, and contains the starting address of the channel-specic parameter
area (address of TBASE). The 5 most-signicant bits are taken from TSATRx, and the 6 least-
signicant bits are always internally set to zero. For the MSC operation, the addressing range is
2 Kbytes.
Mask(0–7)
Mask bits—These 8 bits identify the valid bits in this time slot for subchanneling support. For 8-bit
resolution, all mask bits should be set to 1. Any unmasked bit (1) is processed in the receiver for a
valid time slot. Any masked bit (0) is ignored by the receiver for a valid channel and no bit counter is
affected.
Table 9-2. Time Slot Assignment Table Entry Fields for Transmit (MSC)
Name
Description
V
Valid bit—The valid bit indicates whether this time slot is valid.
0 Logic 1 is transmitted. If the Tx signal of the TDM interface is programmed to be an open drain
output (port B programming), other devices can transmit on nonvalid time slots.
1 Data is transmitted from its associated buffer in combination with the mask bit settings.
W
Wrap bit—The wrap bit identies the last entry in TSATTx.
0 This is not the last time slot in the frame.
1 The RISC processor wraps around and handles time slot 0 or the rst 8 bits of data in the SCC in
the next request. The next request is identied by a frame synchronization pulse.
L
Last bit—Identies the last subchannel in a time slot.
0 This is not the last subchannel in the time slot.
1 This is the last sub channel within an 8-bit time slot.The RISC processor handles the next time
slot transferred to the TSA in the next request.
Tx channel
pointer
This eld of the TSATTx entry identies a data channel which is routed to this time slot. The actual
channel pointer is 11 bits long, and contains the starting address of the channel-specic parameter
area (address of TBASE). The 5 most signicant bits are taken from TSATTx channel pointer eld,
and the 6 least signicant bits are always internally set to zero. For MSC protocol, the addressing
range is 2 Kbytes.
Mask(0–7)
Mask bits—Identies the valid bits in this time slot for subchanneling support. For 8-bit resolution, all
mask bits should be set to 1. For a valid channel with an unmasked bit (1), the bit position is lled
according to the protocol. A valid channel with a masked bit (0) transmits a logic high (1).
Table 9-1. Time Slot Assignment Table Entry Fields for Receive (MSC) (Continued)
Field
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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