參數(shù)資料
型號(hào)： MC68MH360ZP25VL
廠商： Freescale Semiconductor
文件頁數(shù)： 132/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC ETHER 25MHZ 357PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 357-BGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 5. Buffer Descriptors
5.2 Transmit Buffer Descriptor
Figure 5-3 shows the transmit buffer descriptor.
Notes: Entries in boldface must be initialized by the user.
For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 5-3. Transmit Buffer Descriptor (TxBD)
Table 5-2 describes the individual elds of a transmit buffer descriptor. Boldfaced entries
must be initialized by the user.
0123456789
10
11
12
13
14
15
OFFSET + 0
R
—
WI
L
TC
CM
—
UB
———
PAD
OFFSET + 2
DATA LENGTH
OFFSET + 4
Tx DATA BUFFER POINTER
OFFSET + 6
Table 5-2. Transmit Buffer Descriptor (TxBD) Field Descriptions
Field
Name
Description
0
R
Ready
0 The data buffer associated with this buffer descriptor is not ready for transmission. The user
can manipulate this buffer descriptor or its associated data buffer. The CPM clears this bit
after the buffer has been transmitted or after an error condition is encountered.
1 The data buffer, which has been prepared for transmission by the user, has not been
transmitted or is being transmitted. If R = 1, the user cannot write to elds of this buffer
descriptor.
1—
—
2
W
Wrap (nal buffer descriptor in table)
0 This is not the last buffer descriptor in the TxBD table.
1 This is the last descriptor in the Tx buffer descriptor table. After this buffer is used, the CPM
transmits data from the rst buffer descriptor in the table (the buffer descriptor pointed to by
TBASE). The number of TxBDs in this table is programmable and is determined only by the
wrap bit and the overall space constraints of the dual-ported RAM.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 TXB in the circular interrupt table entry is set when the controller services this buffer. This bit
can cause an interrupt (if enabled).
4
L
Last
0 This is not the last buffer in the frame.
1 This is the last buffer in the current frame.
5
TC
Tx CRC (HDLC mode only). This bit is valid only when L = 1; otherwise, it is ignored.
0 Transmit the closing ag after the last data byte. This setting can be used for testing purposes
to send an erroneous CRC after the data.
1 Transmit the CRC sequence after the last data byte.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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