參數(shù)資料
型號： MC68MH360ZP25VL
廠商： Freescale Semiconductor
文件頁數(shù)： 89/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC ETHER 25MHZ 357PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 357-BGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
06
MRBLR
16
Maximum receive buffer length—This host-initialized entry denes the
maximum number of bytes written to a receive buffer before moving to the next
buffer for this channel. This parameter is only valid in HDLC mode.
The buffer area allocated in memory for each buffer is MRBLR + 4. The QMC
adds another long word if non-octet-aligned frames are received in HDLC
operation. The non-octet information is written only to the last buffer of a frame,
but it can happen in any buffer. See Section 5.1, “Receive Buffer Descriptor,” for
more information.
As the QMC works on long-word alignment, MRBLR value should be a multiple
of 4 bytes.
08
Tx_S_PTR
16
Tx time slot assignment table pointer (SCC base + 60 in normal mode; SCC
base + 20 for common Rx & Tx time slot assignment tables)—This global QMC
parameter denes the start value of the TSATTx table. The TSATTx table in the
global multichannel parameter listing starts by default at SCC base + 60.
Tx_S_PTR lets the user move the starting address of this table. If the same
routing and masking are used for the transmitter and receiver, the tables can be
overlaid, so Tx_S_PTR can point to SCC base + 20. This parameter is an offset
from DPRBASE. This table must be present only once per SCC global area.
Other SCCs can access this location.
0A
RxPTR
16
Rx pointer (initialize to SCC base + 20)—This global QMC parameter is a RISC
variable that points to the current receiver time slot. The host must initialize this
pointer to the starting location of TSATRx. The RISC processor increments this
pointer whenever it completes the processing of a received time slot.
0C
GRFTHR
16
Global receive frame threshold—Used to reduce interrupt overhead when many
short HDLC frames arrive, each causing an RXF interrupt. GRFTHR can be set
to limit the frequency of interrupts. Note that the RXF event is written to the
interrupt table on each received frame, but GINT is set only when the number of
RXF events (by all channels) reaches the GRFTHR value. GRFTHR can be
changed on the y. For information about exception handling, see Chapter 4,
“QMC Exceptions.”
0E
GRFCNT
16
Global receive frame count (initialized GRFCNT = GRFTHR)—A down-counter
used to implement the GRFTHR feature. GRFCNT decrements for each frame
received. No other receiver interrupts affect this counter. The counter value is
set to the threshold during initialization. GRFCNT is automatically reset to the
GRFTHR value by the CPM after a global interrupt.
10
INTBASE
32
Multichannel interrupt base address (host-initialized)—This pointer contains the
starting address of the interrupt circular queue in external memory. Each entry
contains information about an interrupt request that has been generated by the
QMC to the host. Each SCC operating in QMC mode has its own interrupt table
in external memory.
See Chapter 4, “QMC Exceptions.”
14
INTPTR
32
Multichannel interrupt pointer (host-initialized)—This global parameter holds the
address of the next QMC interrupt entry in the circular interrupt table. The RISC
processor writes the next interrupt information to this entry when an exception
occurs. The host must copy the value of INTBASE to INTPTR before enabling
interrupts.
Table 2-1. Global Multichannel Parameters (Continued)
Offset
to
SCC
Base
Name
Width
(Bits)
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68MH360ZP33K 制造商:Freescale Semiconductor 功能描述:MULTI HDLC QUICC32 - Trays
MC68MH360ZP33L 功能描述:IC MPU 32BIT QUICC 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
MC68MH360ZP33LR2 功能描述:IC MPU QUICC 33MHZ 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤
MC68MH360ZQ25L 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68MH360ZQ25LR2 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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