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| 型號： | MC68MH360ZP25VL |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 92/158頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC ETHER 25MHZ 357PBGA |
| 標準包裝： | 44 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 25MHz |
| 電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BGA |
| 供應商設備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
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Chapter 2. QMC Memory Organization
Table 2-2 describes the elds in the time slot assignment table for receive.
Table 2-3 describes the elds in the time slot assignment table for transmit.
Table 2-2. Time Slot Assignment Table Entry Fields for Receive Section
Field
Description
V
Valid bit—The valid bit indicates whether this time slot is valid.
0 The data in this 8-bit time slot is totally ignored and not written to any buffer.
1 The data in this 8-bit time slot is valid and written to the current buffer, pointed to by the channel
pointer entry, after protocol processing (e.g. zero deletion in HDLC). Individual bits can be
masked out as described later.
W
Wrap bit—Identies the last entry in TSATRx.
0 This is not the last time slot in the frame.
1 The RISC processor wraps around and handles time slot 0 or the rst 8 bits transferred from the
TSA in the next request. The next request is identied by a frame synchronization pulse.
Rx channel
pointer
This 6-bit eld of the TSATRx entry identies the data channel routed to this time slot. The actual
channel pointer is 12 bits long, and contains the starting address of the channel-specic parameter
area (address of RBASE). The 6 most-signicant bits are taken from the TSATRx channel pointer
eld, and the 6 least-signicant bits are always internally set to zero. For the MH360, the most-
signicant bit must be set to zero, as the addressing range is 2 Kbytes.
Mask(0–7)
Mask bits—These 8 bits identify the valid bits in this time slot for subchanneling support. For 8-bit
resolution, all mask bits should be set to 1. Any unmasked bit (1) is processed in the receiver for a
valid time slot. Any masked bit (0) is ignored by the receiver for a valid channel and no bit counter is
affected.
Table 2-3. Time Slot Assignment Table Entry Fields for Transmit Section
Name
Description
V
Valid bit—The valid bit indicates whether this time slot is valid.
0 Logic 1 is transmitted. If the Tx signal of the TDM interface is programmed to be an open drain
output (port B programming), other devices can transmit on nonvalid time slots.
1 Data is transmitted from its associated buffer in combination with the mask bit settings.
W
Wrap bit—The wrap bit identies the last entry in TSATTx.
0 This is not the last time slot in the frame.
1 The RISC processor wraps around and handles time slot 0 or the rst 8 bits of data in the SCC in
the next request. The next request is identied by a frame synchronization pulse.
Tx channel
pointer
This 6-bit eld of the TSATTx entry identies the data channel routed to this time slot. The actual
channel pointer is 12 bits long, and contains the starting address of the channel-specic parameter
area (address of TBASE). The 6 most-signicant bits are taken from the TSATTx channel pointer
eld, and the 6 least-signicant bits are always internally set to zero. For the MH360 the most-
signicant bit must be set to zero, as the addressing range is 2 Kbytes.
Mask(0–7)
Mask bits—Identies the valid bits in this time slot for subchanneling support. For 8-bit resolution, all
mask bits should be set to 1. For a valid channel with an unmasked bit (1), the bit position is lled
according to the protocol. A valid channel with a masked bit (0) transmits a logic high (1).
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For More Information On This Product,
Go to: www.freescale.com
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| MC68MH360ZP33K | 制造商:Freescale Semiconductor 功能描述:MULTI HDLC QUICC32 - Trays |
| MC68MH360ZP33L | 功能描述:IC MPU 32BIT QUICC 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68MH360ZP33LR2 | 功能描述:IC MPU QUICC 33MHZ 357-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，FCBGA 供應商設備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68MH360ZQ25L | 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68MH360ZQ25LR2 | 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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