- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3972 > MC7448VU667NC (Freescale Semiconductor)IC MPU RISC 32BIT 360-FCCBGA PDF資料下載
參數(shù)資料
| 型號： | MC7448VU667NC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 10/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 32BIT 360-FCCBGA |
| 標準包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 667MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBGA，F(xiàn)CCBGA |
| 供應商設備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
18
Freescale Semiconductor
Electrical and Thermal Characteristics
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
tKHOZ
—1.8
ns
5
SYSCLK to TS high impedance after precharge
tKHTSPZ
—1
tSYSCLK
3, 4, 5
Maximum delay to ARTRY/SHD0/SHD1 precharge
tKHARP
—1
tSYSCLK
3, 5, 6, 7
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
tKHARPZ
—2
tSYSCLK
3, 5, 6, 7
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-
Ω load (see Figure 4). Input and output timings are measured at
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V)
relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the
input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for
inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
3. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and precharged high
before returning to high impedance, as shown in Figure 6. The nominal precharge width for TS is tSYSCLK, that is, one clock
period. Since no master can assert TS on the following clock edge, there is no concern regarding contention with the
precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The
high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low
in the first clock following AACK will then go to high impedance for a fraction of a cycle, then negated for up to an entire cycle
(crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for ARTRY is 1.0 tSYSCLK;
that is, it should be high impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY.
Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning two cycles after TS.
Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire
cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is
1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).
8. BMODE[0:1] and BVSEL[0:1] are mode select inputs. BMODE[0:1] are sampled before and after HRESET negation.
BVSEL[0:1] are sampled before HRESET negation. These parameters represent the input setup and hold times for each
sample. These values are guaranteed by design and not tested. BMODE[0:1] must remain stable after the second sample;
BVSEL[0:1] must remain stable after the first (and only) sample. See Figure 5 for sample timing.
Table 9. Processor Bus AC Timing Specifications1 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol 2
All Speed Grades
Unit
Notes
Min
Max
相關PDF資料 |
PDF描述 |
|---|---|
| MC7448VU600NC | IC MPU RISC 32BIT 360-FCCBGA |
| MC7448VU1700LC | IC MPU RISC 32BIT 360-FCCBGA |
| FMM36DREI | CONN EDGECARD 72POS .156 EYELET |
| HSC60DTEF | CONN EDGECARD 120POS .100 EYELET |
| FMM36DRES | CONN EDGECARD 72POS .156 EYELET |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC7448VU667ND | 功能描述:微處理器 - MPU APL8 RV2.2.1 1.0V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC7448VU800N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC7448 Hardware Specifications |
| MC7448VU800ND | 制造商:Freescale Semiconductor 功能描述:MPU MPC74XX RISC 64BIT 90NM 800MHZ 360FCCBGA - Tape and Reel |
| MC7448VU867N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC7448 Hardware Specifications |
| MC7448VU867NC | 功能描述:IC MPU RISC 32BIT 360-FCCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC74xx 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應商設備封裝:783-FCPBGA（29x29） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復。