參數(shù)資料
型號： MC7448VU667NC
廠商： Freescale Semiconductor
文件頁數(shù)： 60/60頁
文件大?。?/td> 0K
描述： IC MPU RISC 32BIT 360-FCCBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 667MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 360-CBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
9
General Parameters
4
General Parameters
The following list summarizes the general parameters of the MPC7448:
Technology
90 nm CMOS SOI, nine-layer metal
Die size
8.0 mm
× 7.3 mm
Transistor count
90 million
Logic design
Mixed static and dynamic
Packages
Surface mount 360 ceramic ball grid array (HCTE)
Surface mount 360 ceramic land grid array (HCTE)
Surface mount 360 ceramic ball grid array with lead-free spheres (HCTE)
Core power supply
1.30 V
(1700 MHz device)
1.25 V
(1600 MHz device)
1.20 V
(1420 MHz device)
1.15 V
(1000 MHz device)
I/O power supply
1.5 V, 1.8 V, or 2.5 V
5
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC7448.
5.1
DC Electrical Characteristics
The tables in this section describe the MPC7448 DC electrical characteristics. Table 2 provides the
absolute maximum ratings. See Section 9.2, “Power Supply Design and Sequencing,” for power
sequencing requirements.
Table 2. Absolute Maximum Ratings 1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.4
V
2
PLL supply voltage
AVDD
–0.3 to 1.4
V
2
Processor bus supply voltage
I/O Voltage Mode = 1.5 V
OVDD
–0.3 to 1.8
V
3
I/O Voltage Mode = 1.8 V
–0.3 to 2.2
3
I/O Voltage Mode = 2.5 V
–0.3 to 3.0
3
Input voltage
Processor bus
Vin
–0.3 to OVDD + 0.3
V
4
JTAG signals
Vin
–0.3 to OVDD + 0.3
V
Storage temperature range
Tstg
– 55 to 150
C
Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. See Section 9.2, “Power Supply Design and Sequencing” for power sequencing requirements.
3. Bus must be configured in the corresponding I/O voltage mode; see Table 3.
4. Caution: Vin must not exceed OVDD by more than 0.3 V at any time including during power-on reset except as allowed by
the overshoot specifications. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
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