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| 型號： | MC7448VU867NC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 37/60頁 |
| 文件大小： | 0K |
| 描述： | IC MPU RISC 32BIT 360-FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
42
Freescale Semiconductor
System Design Information
9.4
Output Buffer DC Impedance
The MPC7448 processor bus drivers are characterized over process, voltage, and temperature. To measure
Z0, an external resistor is connected from the chip pad to OVDD or GND. The value of each resistor is
Figure 20. Driver Impedance Measurement
The output impedance is the average of two components—the resistances of the pull-up and pull-down
devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the
pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high,
SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then
becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value.
Then, Z0 = (RP + RN)/2.
Table 15 summarizes the signal impedance results. The impedance increases with junction temperature
and is relatively unaffected by bus voltage.
9.5
Pull-Up/Pull-Down Resistor Requirements
The MPC7448 requires high-resistive (weak: 4.7-K
Ω) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7448 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being factory test pins must be pulled up to OVDD or down to GND to ensure
proper device operation. The pins that must be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the
pins that must be pulled down to GND are L1_TSTCLK and TEST[4]. The CKSTP_IN signal should
Table 15. Impedance Characteristics
At recommended operating conditions. See Table 4
Impedance
Processor Bus
Unit
Z0
Typical
33–42
Ω
Maximum
31–51
Ω
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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