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| 型號： | MC7448VU867NC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 32BIT 360-FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
43
System Design Information
likewise be pulled up through a pull-up resistor (weak or stronger: 4.7–1 K
Ω) to prevent erroneous
assertions of this signal.
In addition, the MPC7448 has one open-drain style output that requires a pull-up resistor (weak or
stronger: 4.7–1 K
Ω) if it is used by the system. This pin is CKSTP_OUT.
BVSEL0 and BVSEL1 should not be allowed to float, and should be configured either via pull-up or
pull-down resistors or actively driven by external logic. If pull-down resistors are used to configure
BVSEL0 or BVSEL1, the resistors should be less than 250
Ω (see Table 11). Because PLL_CFG[0:5]
must remain stable during normal operation, strong pull-up and pull-down resistors (1 K
Ω or less) are
recommended to configure these signals in order to protect against erroneous switching due to ground
bounce, power supply noise, or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7448
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7448 or by other receivers in the system. These signals can be pulled up
through weak (10-K
Ω) pull-up resistors by the system, address bus driven mode enabled (see the
MPC7450 RISC Microprocessor Family Users’ Manual for more information on this mode), or they may
be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw.
Preliminary studies have shown the additional power draw by the MPC7448 input receivers to be
negligible and, in any event, none of these measures are necessary for proper device operation. The
snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If address or data parity is not used by the system, and respective parity checking is disabled through HID1,
the input receivers for those pins are disabled and do not require pull-up resistors, therefore they may be
left unconnected by the system. If extended addressing is not used (HID0[XAEN] = 0), A[0:3] are unused
and must be pulled low to GND through weak pull-down resistors; additionally, if address parity checking
is enabled (HID1[EBA] = 1) and extended addressing is not used, AP[0] must be pulled up to OVDD
through a weak pull-up resistor. If the MPC7448 is in 60x bus mode, DTI[0:3] must be pulled low to GND
through weak pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups or require that those signals be otherwise driven by the system during inactive periods. The data
bus signals are D[0:63] and DP[0:7].
9.6
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 standard specification, but is typically provided on all processors that implement the
PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK
and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted
during power-on reset. Because the JTAG interface is also used for accessing the common on-chip
processor (COP) function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
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