參數(shù)資料
型號： MC8641DHX1250HE
廠商： Freescale Semiconductor
文件頁數(shù)： 58/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標準包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.25GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
33
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 10 shows the GMII transmit AC timing diagram.
Figure 10. GMII Transmit AC Timing Diagram
8.2.2.2
GMII Receive AC Timing Specifications
Table 29 provides the GMII receive AC timing specifications.
GTX_CLK data clock fall time (80%-20%)
tGTXF
2
——
1.0
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII
transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input
signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect
to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Table 29. GMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period
tGRX
3
—8.0
—
ns
RX_CLK duty cycle
tGRXH/tGRX
40
—
60
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.5
—
ns
RX_CLK clock rise time (20%-80%)
tGRXR
2
——
1.0
ns
Table 28. GMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
GTX_CLK
TXD[7:0]
tGTKHDX
tGTX
tGTXH
tGTXR
tGTXF
tGTKHDV
TX_EN
TX_ER
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