Analog-to-Digital Converter (ADC)
MC68HC908JL16 Data Sheet, Rev. 1.1
128
Freescale Semiconductor
There are some situations where external system activity causes radiated or conducted noise emissions
or excessive VDD noise is coupled into the ADC10. In these cases, or when the MCU cannot be placed
in wait or I/O activity cannot be halted, the following recommendations may reduce the effect of noise on
the accuracy:
Place a 0.01
F capacitor on the selected input channel to V
REFL or VSSA (if available). This will
improve noise issues but will affect sample rate based on the external analog source resistance.
Operate the ADC10 in stop mode by setting ACLKEN, selecting the channel in ADCSC, and
executing a STOP instruction. This will reduce VDD noise but will increase effective conversion time
due to stop recovery.
Average the input by converting the output many times in succession and dividing the sum of the
results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
Reduce the effect of synchronous noise by operating off the asynchronous clock (ACLKEN=1) and
averaging. Noise that is synchronous to the ADCK cannot be averaged out.
9.3.4.4 Code Width and Quantization Error
The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points from one code to the next. The ideal code width for an N bit converter (in this case N can be 8 or
10), defined as 1LSB, is:
1LSB = (VREFH–VREFL) / 2
N
Because of this quantization, there is an inherent quantization error. Because the converter performs a
conversion and then rounds to 8 or 10 bits, the code will transition when the voltage is at the midpoint
between the points where the straight line transfer function is exactly represented by the actual transfer
function. Therefore, the quantization error will be ± 1/2LSB in 8- or 10-bit mode. As a consequence,
however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF
or $3FF) is 1.5LSB.
9.3.4.5 Linearity Errors
The ADC10 may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the user should be aware of them because they affect overall accuracy. These errors are:
Zero-Scale Error (EZS) (sometimes called offset) — This error is defined as the difference between
the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first
conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is
used.
Full-Scale Error (EFS) — This error is defined as the difference between the actual code width of
the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the
difference between the actual $3FE code width and its ideal (1LSB) is used.
Differential Non-Linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
Integral Non-Linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition
voltage to a given code and its corresponding ideal transition voltage, for all codes.
Total Unadjusted Error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function, and therefore includes all forms of error.