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| 型號： | MC92602ZTA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196 |
| 文件頁數(shù)： | 28/102頁 |
| 文件大小： | 1581K |
| 代理商： | MC92602ZTA |
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MOTOROLA
Chapter 3. Receiver
3-3
Receiver Interface Signals
3.2
Receiver Interface Signals
This section describes the interface signals of the MC92602 receiver. Each signal is
described in Table 3-1, including its name, function, direction, and active state. The signal
names use the letter ‘x’ as a place holder for the link identifier letters ‘A’ through ‘D.’
Internal signals are not available at the I/O of the device, but are presented to illustrate
device operation.
Table 3-1. MC92602 Receiver Interface Signals
Signal Name
Description
Function
Direction
Active
State
RECV_x_[3:0]
Received nibble
If TBIE is low, these are 4 bits of uncoded
data received. Bits 3–0 on the rising edge of
clock. Bits 7–4 on the falling edge of clock.
If TBIE is high, these 4 bits are coded data
received. Bits 3–0 on the rising edge of
clock. Bits 8–5 on the falling edge of clock.
Output
—
RECV_x_K
Special data indicator
If TBIE is low, both rising and falling edge
states are used to encode status out, see
Table 3-4. If TBIE is high, this is data bit 4 on
the rising edge and data bit 9 on the falling
edge.
Output
—
RECV_x_ERR
Receiver error
Receiver status out. If TBIE is low, it is used
in conjunction with RECV_x_K. If TBIE is
high, then it is the only status bit. See
Table 3-6 and Table 3-7.
Output
—
RECV_x_CLK
Receiver clock
Internally generated clock used for reading
receiver outputs. This signal may be derived
from the REF_CLK, receiver A’s recovered
clock, or this receiver’s recovered clock.
Output
—
TBIE
Ten-bit interface enable
Indicates that the receiver interface is in
ten-bit mode and that the 8B/10B decoder is
bypassed.
Input
High
HSE
Half-speed enable
Indicates to operate link at half speed. Both
data and link interfaces run at half speed.
Input
High
WSE
Word synchronization
enable
Indicates that all enabled receivers are
being used in unison to receive
synchronized data.
Input
High
BSYNC
Byte alignment mode
Indicates that byte alignment is required. If
low, no byte alignment is done.
Input
—
RCCE
Recovered clock enable
Indicates that the output data is
synchronized to a recovered byte clock.
Input
High
REPE
Repeater mode enable
Test feature only. Must be disabled (low)
during normal operation.
Input
High
RECV_REF_A
Receiver A clock enable
Indicates that if RCCE is also high that the
data will be synchronized to channel A’s
recovered clock.
Input
High
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