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參數(shù)資料
| 型號： | MC92602ZTA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196 |
| 文件頁數(shù)： | 58/102頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | MC92602ZTA |
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MOTOROLA
Chapter 6. Test Features
6-5
System Accessible Test Modes
This implementation of the 23-bit PN generator and analyzer uses the polynomial:
f = 1 + x5 + x23
The total mismatch error count is reset to zero when BIST mode is entered. The count is
updated continuously while in BIST mode. The value of the count is presented on the
receiver interface signals: RECV_x_3–RECV_x_0 (as interpreted and shown in Table 3-4),
making up the 8-bit error count, ordered bits 7–0, respectively. The value of the count is
sticky in that the count will not wrap to zero on overflow, but rather, stays at the maximum
count value (11111111).
The RECV_x_ERR and RECV_x_K signals (as interpreted and shown in Table 6-5), have
special meaning during this test mode. They report the status of the receiver and PN
the values on RECV_x_ERR and RECV_x_K, respectively, on the rising edge of the
recovered clock. E1 and K1 are the values of RECV_x_ERR and RECV_x_K, respectively,
on the falling edge of the recovered clock.
The BIST sequence makes use of the 8B/10B encoder/decoder. Therefore, this test mode
overrides the setting on TBIE signal and forces byte interface mode. Additionally, the BIST
sequence requires that a normal byte alignment mode be used. The setting of BSYNC is
overridden, forcing the device into the byte aligned mode (forces BSYNC high internally).
BIST is run at the speed indicated by the frequency of the reference clock and by the speed
range selected by half-speed mode (HSE). The settings of WSE, RCCE, and
RECV_REF_A are not altered and BIST will follow their setting.
In order to properly use this test mode, the system must provide the proper stimulus in a
special sequence. The sequence is as follows:
1. Enter test mode by setting the test mode inputs as described in Table 6-4.
2. Transmit 4096 IDLEs (K28.5 characters).
3. Transmit to the receiver an 8B/10B encoded PN sequence as described above.
Table 6-5. BIST Error Codes
E0
E1
K0
K1
Description
Low
Don’t care
Don’t care BIST running, no PN mismatch this character.
Low
High
Low
BIST running, PN mismatch error this character.
Low
High
Low
High
Receiver byte/word synchronized, PN analyzer is not locked.
High
Low
Don’t care
Don’t care Not byte sync: The receiver is in startup or has lost byte alignment
and is searching for alignment.
High
Don’t care
Don’t care Not word sync: The receiver is byte synchronized but has not
achieved or has lost word alignment and is searching for
alignment.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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