參數(shù)資料
型號(hào)： MC92602ZTA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196
文件頁(yè)數(shù)： 49/102頁(yè)
文件大?。?/td> 1581K
代理商： MC92602ZTA
5-2
MC92602 SerDes Reference Manual
MOTOROLA
Startup
The clock inputs REF_CLK_P and REF_CLK_N are normally driven with a differential
clock source. However, the reference clock may also be driven with a single-ended source.
In this situation, the REF_CLK_P signal is driven by the single-ended clock source and the
REF_CLK_N signal is held at the HSTL reference voltage as defined in Section 5.8,
“HSTL Reference Voltage Recommendation.” The REF_CLK_N signal may be connected
to its own reference voltage circuit or may share the reference voltage circuit used for the
HSTL_VREF signal, if board layout allows.
5.2
Startup
The MC92602 begins a startup sequence on application of the reference clock
(REF_CLK_N/P input) to the device. This is considered a ‘cold’ startup. The cold startup
sequence is as follows:
1. PLL startup
2. Receiver initialization and byte alignment
3. Word alignment (if enabled)
4. Run
The expected duration of each step in the startup sequence is shown in Table 5-2. A cold
startup can be initiated at any time by setting RESET low. It is recommended that RESET
be low at initial startup, however, it is not strictly required.
5.3
Standby Mode
Standby mode puts the MC92602 into a low-power, inactive state. When STNDBY is
asserted high, the device will force all transmitter link outputs to their disabled state as
defined in Section 2.3.3, “Transmit Driver Operation,” and will disable all internal
clocking. An important feature of standby mode is that the internal PLL is not disabled. It
remains operating and locked to the reference clock. This greatly reduces the time needed
to recover from standby mode to run mode, as only the receiver initialization and word
alignment startup steps are required.
Table 5-2. Startup Sequence Step Duration
Startup Step
Typical Duration
(in Bit Times)
Notes
PLL startup
10,2400 + 25
s—
Receiver initialization
50
WSE = low
160
WSE = high
Word alignment
50
WSE = low
160
WSE = high
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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